Lifetime Service
  • Installed: 01/30/2008
  • Retired: 01/04/2010
  • Hours: 520
  • Jobs: 610
  • Users: 6

Overview of Brutus

Brutus was an experimental FPGA resource provided by the Northwest Indiana Compuational Grid (NWICG) through ITaP. Brutus consisted of an SGI Altix 450 with two SGI RC100 blades with two FPGAs each, for a total of 4 FPGAs. Using Brutus effectively required careful code development in either VHDL or Mitrion-C, but did result in significant performance increases. BLAST was been benchmarked on Brutus at 70x typical general-purpose CPU performance.

Detailed Hardware Specification
Number of Nodes Processors per Node Cores per Node Memory per Node Retired in
2 One Virtex 4 LX200 Dual-FPGA 2 80 MB QDR SDRAM 2010

Brutus ran SuSE Linux Enterprise Server 10 and used Condor for resource and job management.

FPGA algorithms were serialized, placed, and routed (analogous to compilation) and then registered for use by Brutus jobs from the frontend node portia.rcac.purdue.edu, from which jobs were also submitted. Mitrionics' Mitrion-C compiler for FPGA algorithm development was provided, as well as Xilinx VHDL tools. Pre-SPRed bitcode could also be used. Some algorithms, such as BLAST, were provided pre-installed by ITaP.