Purdue hosting Intel parallel programming, acceleration workshop

September 4, 2014  8:30am – 4:00pm
STEW 320

Purdue will host a parallel programming training session by Intel in September designed to assist researchers and software developers with updating their code to take full advantage of hardware like Intel’s Xeon processor and Xeon Phi coprocessor, both features of Purdue’s newest research supercomputer the Conte cluster.

The one-day training session for Purdue and non-Purdue faculty, staff and students, as well as area professional software engineers and architects, will take place from 8:30 a.m. to 4 p.m. on Thursday, Sept. 4, in the Stewart Center, Room 320. Continental breakfast and lunch will be served.

Space is limited so participants should register soon. Participants can get more information and register through Intel. There is no cost to register. Intel and ITaP are sponsoring the event.

The training session will cover such topics as:

  • An overview of parallel programming frameworks and optimization guidelines for multicore processors and many-core coprocessors.
  • Tips for quick porting and development of high-performance computing software applications.
  • Real-life examples of code and optimization techniques.

The goal is for participants to leave with the foundation needed for modernizing their code to take advantage of parallel architectures found in the Xeon processor and Phi coprocessor.

Staff from ITaP Research Computing (RCAC) will be available to interact with people attending the session, says Stephen Harrell, a senior high-performance computing system administrator who coordinates training for ITaP Research Computing (RCAC), which operates Conte and Purdue’s other Community Cluster Program supercomputers for faculty researchers and their students.

For more information, email rcac-help@purdue.edu.

Originally posted: August 11, 2014  9:07pm